Wasga Architect: the multi-FPGA board synthesis tool

Custom FPGA boards are designed to implement specific designs and applications to reach the highest performance. Commonly, boards are tailored regarding user interfaces specification. In most cases complex designs do not fit to only one FPGA and grouping multiple FPGA on the same board is a must. Interconnecting multiple FPGA (amount of pair physical traces) is critical and, in most cases, the interconnect distribution is done in a balanced way. This choice is risky as it may not fit design nature and penalizes the final resulting system performance. Flexras revisits multi-FPGA board design and proposes to do it jointly with design implementation. Thus, it tailors interconnect distribution according to design partitioning and routing results to get the best performances.

For this purpose, Flexras Technologies launches Wasga Architect™ suite, a unique technology, synthesizing design-driven multi-FPGA boards. Wasga Architect takes the user design as input, partitions it, according to the user-selected FPGA family, and generates the corresponding multi-FPGA board netlist which most fits the design. Wasga Architect can answer questions such as: which board netlist has the highest frequency? Which board netlist is the less expensive? Which board netlist best fits this particular objective? Wasga Architect enables multi-FPGA board netlists space exploration to select the most suitable one to user exact needs.

Partitioning

Partitioning consists in splitting design between FPGAs to meet available logic resources. In this early stage, the board is not yet specified. The only available informations are the FPGA family (logic capacity, pakage and pins number) and the board interfaces (PCI, Ethernet, DRAM, etc.). The partitioner specifies the required number of FPGA and attempts to constraint the number of crossing signals to meet the number of available FPGA user pins. After this phase, we obtain the number of FPGA and the assigned design instances to each one.

Interconnect Synthesis

The remaining task is to specify interconnect distribution between FPGA pairs. The objective is to distribute traces amount to reduce the multiplexing ratio if it happens. This is done mainly by the timing-driven traces routing algorithms of Wasga. After this phase, we obtain the detailed netlist of the multiple FPGA board including FPGA devices and interfaces components.

Floorplanning

This phase consists in specifying FPGA orientations and positions on the board regarding the generated netlist and attractions to the system interfaces (pci, ethernet, RAM …)