WE OFFER THE BEST TECHNOLOGY
TO OUR CUSTOMERS
Complex and large SoC designs do not fit to only one FPGA. The way the design is partitioned between FPGA has a determinant effect on the multi-FPGA system performance. Flexras revisits the partitioning problem in an innovative way by considering timing aspects in early stages and unifying competitive objectives to obtain optimal solution. The following optimization features present the advanced Wasga technology:
| Smart design hierarchy management: Selective preservation of hierarchical blocks - To reduce considerably partitioning problem complexity - To keep the global netlist view during the partitioning process |
| Multiple clock domains management - Each clock-domain paths are optimized independently |
| Timing-driven partitioning - Critical paths crossing FPGA are reduced |
| Interconnect-driven partitioning - Multiplexing ratio is reduced when crossing signals exceed FPGA pins |
| Timing-driven routing - Critical signals with low slacks are not multiplexed |
| Through FPGA routing - Overcrowded board traces are avoided to reduce multiplexing ratio |
| Timing graph back annotation (based on FPGA timing tools) - To get accurate internal FPGA delays estimation |
| Timing budgeting for FPGA PnR - To meet prototyping system clock frequency |
| Optimized synchronous inter-chips communication IPs (SERDES/LVDS) - Reduce wire sharing delay to achieve high system performance |